// Copyright (C) 1953-2022 NUDT
// Verilog module name - signaling_process
// Version: V4.1.0.20221208
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module signaling_process#(parameter local_module_id = 12'd0)
(
    i_clk  ,
    i_rst_n,
    
    iv_port_ptp_enabled   ,
	iv_signaling_period   ,

	iv_hcp_mid            ,
    
    iv_data               ,
    i_data_wr             ,
  
	ov_data               ,
	o_data_wr                                              
);

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n; 
// pkt input
input     [31:0]        iv_port_ptp_enabled;
input     [3:0]         iv_signaling_period  ;

input     [11:0]        iv_hcp_mid     ;

output    [8:0]	        iv_data        ;
output   	            i_data_wr      ;
// pkt output to NMA
output    [8:0]	        ov_data        ;
output   	            o_data_wr      ;
                						          
wire	                w_signaling_generate_pulse_spt2sig ;
wire                    w_first_byte_valid_sig2ope    ;

wire       [8:0]        wv_data_sig2ope;           
wire                    w_data_wr_sig2ope;
wire       [3:0]        wv_ptp_message_type_sig2ope; 

wire       [8:0]        wv_data_opd2srp    ; 
wire                    w_data_wr_opd2srp  ;
opensync_protocol_decapsulate opensync_protocol_decapsulate_inst
(
        .i_clk              (i_clk                   ),
        .i_rst_n            (i_rst_n                 ),
                                                     
        .iv_data            (iv_data           ),
        .i_data_wr          (i_data_wr         ),
         
        .ov_local_cnt_rx    ( ),
        .ov_eth_type        ( ), 
        .ov_tsmp_type       ( ),
        .ov_tsmp_subtype    ( ),
		.ov_osm_id          ( ),
                            
        .ov_data            (wv_data_opd2srp      ),
		.o_data_wr          (w_data_wr_opd2srp    )
);

signaling_receive_process signaling_receive_process_inst
(
        .i_clk              (i_clk                   ),
        .i_rst_n            (i_rst_n                 ),
                                                     
        .iv_data            (wv_data_opd2srp   ),
        .i_data_wr          (w_data_wr_opd2srp ),
                            
        .ov_data            (      ),
		.o_data_wr          (      )
);
   
initiator_request_timing  signaling_period_timing_inst
(
        .i_clk                  (i_clk  ),
        .i_rst_n                (i_rst_n),
 
        .iv_port_ptp_enabled	(iv_port_ptp_enabled),
        .iv_measure_period      (iv_signaling_period  ),		
 
        .o_measure_req          (w_signaling_generate_pulse_spt2sig)
);

signaling_packet_generate #(.local_module_id(local_module_id))signaling_packet_generate_inst
(
    .i_clk                  (i_clk   ),
    .i_rst_n                (i_rst_n ),
	 
	.i_signaling_generate_pulse  (w_signaling_generate_pulse_spt2sig),
	.iv_hcp_mid             (iv_hcp_mid                  ),
 
	.ov_data                (wv_data_sig2ope             ),
	.o_data_wr              (w_data_wr_sig2ope           ),
    .ov_ptp_message_type    (wv_ptp_message_type_sig2ope ),
    .o_first_byte_valid     (w_first_byte_valid_sig2ope  )    
);

opensync_protocol_encapsulate #(.osm_id(8'd0),.local_module_id(local_module_id))opensync_protocol_encapsulate_gnp
(
        .i_clk              (i_clk            ),
        .i_rst_n            (i_rst_n          ),

        .iv_hcp_mid         (iv_hcp_mid             ),
        .iv_opensync_dst_module_id(12'h701),//组播的moduleid.
        
        .iv_data            (wv_data_sig2ope       ),
        .i_data_wr          (w_data_wr_sig2ope     ),
		//.iv_osm_id          (8'b0        ),
		.iv_eth_type        (16'h88f7                    ),
		.iv_ptp_messagetype (wv_ptp_message_type_sig2ope ),
        .iv_local_count_rx  (24'b0                       ),
        .i_diagest_wr       (w_first_byte_valid_sig2ope  ),
        
        .ov_data            (ov_data    ),
        .o_data_wr          (o_data_wr  )
);                
endmodule